“ An efficient VLSI architecture for Iterative Logarithmic Multiplier ” IEEE 4 th International conference on signal processing and integrated networks (SPIN), Amity University, Noida, 2-3 Feb.2017.
Ask for paper“ An Efficient VLSI architecture design for antilogarithmic converter by using the error correction scheme ” IETE International conference on signal processing (ICSP), SATI, vidisha, 11-13 Nov. 2016.
Ask for paper“ An efficient VLSI architecture of multiplier-less 1-D DWT using CSD technique ” IETE International conference on signal processing (ICSP), SATI, vidisha, 11-13 Nov. 2016.
Ask for paper“ Crosstalk mitigation of network on chip: an analytical review ” IEEE International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, pp: 378-383, 3-5 March 2016, DOI: 10.1109/ICEEOT.2016.7755393.
Ask for paper“ The comparative result of symmetric encryption techniques ” ICICIC Global, Springer indexed, Chennai, Dec. 2012.
Ask for paper“ Key Reconfiguration Scheme for DES Algorithm ” ICICIC Global, Springer indexed, Chennai, Dec. 2012.
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